Nintendo Ultra64 Programmer's Manual page 194

LUV
31
LWC2
1 1 0 0 1 0
6
Format:
luv vt[0], offset(base)
Description:
This instruction loads eight consecutive bytes into the upper bytes of eight VU register elements.
The bytes are loaded with their MSB positioned at bit 14 in the register element. See Figure 3-3,
"Packed Loads and Stores," on page 53.
The effective address is computed by adding the
GPR).
This instruction has three load delay slots (results are available in the fourth instruction following
this load). If an attempt is made to use the target register
interlocking will stall the processor until the load is completed.
This instruction could be used to unpack 8-bit pixel data such as RGBA or luma (Y) values.
194
Load Unsigned Packed
into Vector Register
26 25 21 20
base
5
The element specifier
Note:
16 15 11 10
vt LUV
0 0 1 1 1
5 5
offset to the contents of the
element should be 0.
LUV
7 6
element offset
4 7
base
vt
in a delay slot, hardware register
0
register (a SU