Nintendo Ultra64 Programmer's Manual page 165

BGTZ
31 26
BGTZ
0 0 0 1 1 1
6
Format:
bgtz rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot
offset
and the 16-bit
compared to zero. If the contents of general register
to zero, then the program branches to the target address, with a delay of one instruction.
Since the RSP program counter is only 12 bits, only 12 bits of the calculated address are used.
Operation:
T:
T+1: if condition then
Exceptions:
None
Revision 1.0
Branch On Greater Than Zero
25 21 20
rs 0
0 0 0 0 0
5 5
, shifted left two bits and sign-extended. The contents of general register
target  (offset 14
) || offset || 0
15
condition  (GPR[rs]
31
 PC
PC
11...0 11...0
endif
16 15
offset
16
rs
have the sign bit cleared and are not equal
2
= 0) and (GPR[rs]  0
+ target
11...0
BGTZ
0
32
)
rs
are
165