Nintendo Ultra64 Programmer's Manual page 199

MTC0
31 26 25
COP0
0 1 0 0 0 0
6
Format:
mtc0 rt, rd
Description:
The contents of general register
Operation:
data  GPR[rt]
T:
T+1: CPR[0,rd] data
Exceptions:
None
Revision 1.0
Move To
System Control Coprocessor
21 20 16
MT rt
0 0 1 0 0
5 5
rt are loaded into coprocessor register
15 11 10
rd
0 0 0 0 0 0 0 0 0 00
5
MTC0
0
0
11
rd of CP0.
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