Nintendo Ultra64 Programmer's Manual page 197

MFC0
31 26 25
COP0
0 1 0 0 0 0
6
Format:
mfc0 rt, rd
Description:
The contents of coprocessor register
Operation:
data  CPR[0,rd]
T:
T+1: GPR[rt]  data
Exceptions:
None
Revision 1.0
Move From
System Control Coprocessor
21 20 16
MF rt
0 0 0 0 0
5 5
rd
15 11 10
rd
0 0 0 0 0 0 0 0 0 0 0
5
of the CP0 are loaded into general register
MFC0
0
0
11
rt.
197