Nintendo Ultra64 Programmer's Manual page 281

VMUDN
31 26
COP2
0 1 0 0 1 0
6
Format:
vmudn vd, vs, vt
vmudn vd, vs, vt[e]
Description:
The 16-bit elements of vector register
elements of vector register
mid partial product, multiplying a fraction (
Bits 15...0 of the accumulator are clamped to 16 bit signed values and placed into vector register
If an element specification
used as described below.
Revision 1.0
Vector Multiply
of Mid Parital Products
25 24 21 20
1 e vt
1 4 5
vs
, and loaded into the accumulator. This instruction is designed for the
e
is present for vector register
16 15 11 10
vs vd
5
vt
are multiplied on an element-by-element basis to the
vs
) times an integer (
vt
, the selected scalar element(s) of
VMUDN
6 5 0
VMUDN
0 0 0 1 1 0
5 6
vt
).
vd
.
vt
is
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