Nintendo Ultra64 Programmer's Manual page 212

SLLV
31
SPECIAL
0 0 0 0 0 0
Format:
sllv rd, rt, rs
Description:
The contents of general register
bits contained in general register
The result is placed in register
Operation:
s  GP[rs]
T:
GPR[rd] GPR[rt]
Exceptions:
None
212
Shift Left Logical Variable
26 25 21
rs
6 5
4...0
(31–s)...0
20 16 15
rt rd
5 5
rt
are shifted left the number of bits specified by the low-order five
rs
, inserting zeros into the low-order bits.
rd
.
s
|| 0
SLLV
11 10 6 5
0 SLLV
0 0 0 0 0 0 0 0 1 0 0
5
0
6