Nintendo Ultra64 Programmer's Manual page 260

VMACQ
31
COP2
0 1 0 0 1 0
6
Format:
vmacq vd, vs, vt
vmacq vd, vs, vt[e]
Description:
This instruction ignores
(32 << 16) if the accumulator is negative and ACC
positive and ACC
Bits 32...17 of the accumulator are clamped to 16 bit signed values and placed into vector register
vd
.
If an element specification
used as described below.
1
Oddification is performed as described in the MPEG1 specification, ISO/IEC 11172-2.
260
Vector Accumulator
Oddification
26 25 24 21 20
1 e
1 4
vs and vt
is zero; or adding zero if ACC
21
e
is present for vector register
16 15 11 10
vt vs
5 5
inputs, and performs oddification
is zero; adding (-32<<16) if the accumulator is
21
47...21
VMACQ
6 5
vd VMACQ
0 0 1 0 1 1
5 6
1
of the accumulator by adding
are zero or ACC is 1.
21
vt
, the selected scalar element(s) of
0
vt
is