Nintendo Ultra64 Programmer's Manual page 270

VMADN
31
COP2
0 1 0 0 1 0
6
Format:
vmadn vd, vs, vt
vmadn vd, vs, vt[e]
Description:
The 16-bit elements of vector register
elements of vector register
designed for the mid partial product, multiplying a fraction (
Bits 15...0 of the accumulator are clamped to 16 bit signed values and placed into vector register
If an element specification
used as described below.
270
Vector Multiply-Accumulate
of Mid Partial Products
26 25 24 21 20
1 e
1 4
vs
, and added to bits 31...0 of the accumulator. This instruction is
e
is present for vector register
16 15 11 10
vt vs
5 5
vt are multiplied on an element-by-element basis to the
VMADN
6 5
vd VMADN
0 0 1 1 1 0
5 6
vs
) times an integer (
vt
, the selected scalar element(s) of
0
vt
).
vd
.
vt
is