Table of Contents
Advertisement
HARDWARE REFERENCE
3.12
PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)
PLX Technology's PCI 9060 device provides the PCI-SDK Platform with a PCI bus interface, allowing
high-bandwidth data transfer between the PCI-SDK Platform and host or target hardware connected to
the PCI bus. The PCI 9060 has several programmable features designed to allow maximum throughput
on the PCI bus:
•
Bus Mastering
•
PCI interrupts (host-to-PCI 9060 and PCI 9060-to-host)
•
On-chip read and write FIFOs to support PCI burst transfers
•
Eight 32-bit mailbox registers
•
Two 32-bit doorbell registers
•
Two channel, bi-directional DMA
3.12.1
PCI 9060 Configuration
PCI 9060 configuration is a two step process. Local (i960-side) configuration is performed by user code
running on the PCI-SDK Platform. When this code has finished, a bit is set which allows the PCI 9060
to accept PCI accesses from the host system. The host-side configuration is generally handled by start-
up code contained in the BIOS on the host system, although some cases may require that additional
initialization is performed by a device driver or user application.
Registers on the PCI 9060 are divided into four groups. Refer to PLX Technology's PCI 9060 documen-
tation for detailed register descriptions:
•
PCI Configuration Registers
•
Local Configuration Registers
•
Shared Run Time Registers
•
Local DMA Registers
The PCI Configuration, Local Configuration, and Shared Run Time register groups are accessible to
both the local i960 processor and the host system; the Local DMA registers are accessible only to the
local processor. The PCI Configuration registers are initialized by the host system, and need not be
programmed from the i960-side during initialization. Local Configuration registers control the mapping
of memory from the PCI-SDK Platform into PCI space on the host system.
If memory on the PCI-SDK Platform will be accessible from the PCI bus, code running on the PCI-
SDK Platform must initialize several registers in the Local Configuration group. In the Shared Run
Time register group, the Interrupt Control/Status (E8H) and EEPROM Control (ECH) registers must
also be programmed from the i960-side during initialization. When complete, the configuration code
must set the PCI 9060 to allow PCI accesses, and the host initialization will begin.
3-16
Advertisement
Table of Contents
