Intel i960 Series User Manual page 4

CONTENTS
3.9.4 CIO Port C .............................................................................................................................................. 3-14
3.10 NON-VOLATILE PARAMETER MEMORY................................................................................................... 3-14
3.11 SQUALL II MODULE INTERFACE............................................................................................................... 3-14
3.12 PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)................................................................................. 3-16
3.12.1 PCI 9060 Configuration .......................................................................................................................... 3-16
3.12.1.1 Accessing Configuration Registers .................................................................................................. 3-17
3.12.1.2 PCI-to-Local Configuration .............................................................................................................. 3-18
3.12.1.3 RAM Region Configuration .............................................................................................................. 3-19
3.12.1.4 Expansion ROM Region Configuration ............................................................................................ 3-22
3.12.1.5 Memory Region Configuration Examples ........................................................................................ 3-22
3.12.2 Local-to-PCI Configuration ..................................................................................................................... 3-24
3.12.3 Deadlock Configuration .......................................................................................................................... 3-27
3.12.4 Signalling Init Done ................................................................................................................................. 3-28
3.12.5 PCI Interrupts .......................................................................................................................................... 3-28
3.12.5.1 Local PCI Interrupts ......................................................................................................................... 3-29
3.12.6 Mailbox Registers and Doorbell Interrupts .............................................................................................. 3-31
3.12.6.1 Using the Mailbox Registers ............................................................................................................ 3-31
3.12.6.2 Generating Doorbell Interrupts ........................................................................................................ 3-31
3.12.6.3 Receiving Doorbell Interrupts .......................................................................................................... 3-31
3.12.7 DMA Programming ................................................................................................................................. 3-32
3.12.7.1 DMA Non-Chaining Mode ................................................................................................................ 3-32
3.12.7.2 DMA Chaining Mode ....................................................................................................................... 3-33
3.12.7.3 DMA Interrupts ................................................................................................................................ 3-34
CHAPTER 4
THEORY OF OPERATION
4.1 FUNCTIONAL OVERVIEW ............................................................................................................................ 4-1
4.2 CLOCK GENERATION .................................................................................................................................. 4-1
4.3 POWER MONITOR AND RESET................................................................................................................... 4-2
4.4 I/O INTERFACE ............................................................................................................................................. 4-2
4.4.1 Functional Blocks ...................................................................................................................................... 4-3
4.4.2 I/O Control Timing ..................................................................................................................................... 4-3
4.4.3 Data Path .................................................................................................................................................. 4-4
4.4.3.1 Parallel Port ....................................................................................................................................... 4-5
4.4.3.2 Serial Port .......................................................................................................................................... 4-6
4.5 DRAM SUBSYSTEM ...................................................................................................................................... 4-6
4.5.1 Page Mode DRAM SIMM Review ............................................................................................................. 4-6
4.5.1.1 Bank Interleaving ............................................................................................................................... 4-7
4.5.1.2 Wait State Performance .................................................................................................................... 4-7
4.5.2 DRAM Controller Implementation ............................................................................................................. 4-8
4.6 CAS Generation ........................................................................................................................................... 4-10
4.7 Refresh Generation ...................................................................................................................................... 4-10
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