Squall Ii Module Timing; Squall Ii Module Slave Timing - Intel i960 Series User Manual

SQUALL II MODULE INTERFACE
5.6

Squall II Module Timing

The Squall Interface signals are an enhanced set of the i960 Cx processor's bus signals. The interface
has two modes of operation: slave and master.
• In slave mode the processor is accessing devices on the Squall II Module.
• In master mode a Squall II Module based DMA controller is accessing the shared memory.
5.6.1

Squall II Module Slave Timing

This section outlines the signal timing of the Squall II Module interface when the i960 processor is
reading or writing the Squall II Module. The timing for the Squall II Modules in slave mode is difficult
to quantify because of the multitude of i960 processors and frequencies which can be run on the
Cyclone EP. Most designers will only be concerned with a particular processor at a specific range of
frequencies, and will not need to concern themselves with all the possible combinations.
The Cyclone EP local bus and the Squall II Module interface operate like the i960 CA/CF processor's
bus interface, regardless of which i960 processor module is installed. On the Cyclone EP, most of the
Squall II Module signals are directly connected to the i960 processor. Although processors (i.e., Sx, Kx,
Jx) with multiplexed data and address signals are demultiplexed on the processor module. The following
timing diagrams show the timing for reads, writes and burst cycles. Many of the timing parameters are
specific to the processor and frequency used. Refer to the appropriate 80960 data sheet for these
parameters.
Two mandatory conditions must be met by Squall II Module slave hardware. First, some i960
processors do not have internal wait state generation; therefore, the Squall II interface is designed to
always require READY to be returned for all accesses to the Squall II Module address range
(C000 0000H to CFFF FFFFH). Processors with internal wait state generation should be programmed
such that the internal wait state generator is disabled and READY is enabled for region C. Using the
internal wait state generator results in the signal SELSQ not being properly negated at the end of the
access.
The second mandatory function of the Squall II Module circuitry is that READY must be asserted for all
accesses to region C. A timeout circuit is provided but software mistakes are easier to find if they are
not relied on by the Squall II Module hardware.
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