Table of Contents
Advertisement
SQUALL II MODULE INTERFACE
D600A
1
PMCLK
t1
S_ADS
SQxSEL
S_BLAST
t7
S_ADDR
t7
S_BEx
t8
S_W/R
S_DATA
S_READY
NOTE: Diagram shows two wait states; any number of wait states are acceptable.
Figure 5-4. Squall II Slave Read and Write Timing Diagram
5-10
2
3
4
5
t1
t2
t6
t4
t9 t10
6
7
8
t1
t1
t2
t2
t6
t6
t7
t7
t8
t11
t5
9
10
t2
t6
t7
t7
t11
t9 t10
Advertisement
Table of Contents
