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3.12.6
Mailbox Registers and Doorbell Interrupts
The PCI 9060 provides eight 32-bit bi-directional mailbox registers and two 32 bit doorbell registers
(one PCI-to-i960, one i960-to-PCI). These registers can be used for interprocess communication and
synchronization across the PCI bus. Values written to the mailbox registers from one side of the bus can
be retrieved by the appropriate process running on the other side. The PCI 9060 doorbell registers are
bitmapped and can indicate 32 different interrupt sources. Doorbell interrupts are enabled by setting the
appropriate bits in the Interrupt Control and Status Register on the PCI 9060.
3.12.6.1
Using the Mailbox Registers
Mailbox registers are included in the local and PCI memory maps when the PCI-SDK Platform is
present in a host system. Refer to PLX PCI 9060 documentation for Mailbox register locations in local
and PCI space. The Mailboxes latch a value written to them; the value can then be read by a process on
the other side of the bus. Reads to a Mailbox register do not affect the contents (does not clear it).
3.12.6.2
Generating Doorbell Interrupts
Doorbell interrupts to the host system are generated by setting one or more of the bits of the Local-to-
PCI Doorbell Register (E4H). The host processor can read the Doorbell register to determine which bits
are set. More than one bit may be set concurrently, and the PCI interrupt remains asserted as long as at
least one doorbell bit is set. This allows the PCI 9060 to signal as many as 32 different interrupts to the
host processor.
PCI masters can generate doorbell interrupts to the i960 processor by writing the PCI-to-Local Doorbell
Register (E0H). Setting bits in the PCI-to-Local Doorbell Register generates an interrupt to the i960
processor. The PCI 9060 signals an interrupt to the local processor as long as at least one bit is set.
For doorbell interrupts to function, the Interrupt Control and Status Register (E8H) on the PCI 9060
must be programmed to enable the interrupts. For local-to-PCI doorbell interrupts, the PCI Interrupt
Enable and PCI Doorbell Interrupt Enable bits must be set. PCI interrupts must also be enabled and
routed on the host system. For PCI-to-local interrupts, software must set the Local Interrupt Enable and
Local Doorbell Interrupt Enable bits. The Interrupt Control and Status Register also contains bits which
allow software to poll for PCI or local interrupts.
3.12.6.3
Receiving Doorbell Interrupts
Provided that interrupts are enabled on the PCI 9060, a PCI-to-local doorbell interrupt is signalled to the
i960 processor on the PCI 9060 interrupt line (XINT0 on the Cx, Jx, and Hx processors; INT2 on the Kx
and Sx). The i960 processor must then poll the Interrupt Control and Status Register (E8H) on the PCI
9060 to determine the cause of the interrupt. If a doorbell interrupt is detected, software should read the
PCI-to-Local Doorbell Register (E0H) to determine which interrupts are being signalled. Writing a 1 to
an active doorbell bit clears the bit and, if no other doorbell bits are set, clears the interrupt also. If other
doorbell bits are set, the interrupt remains asserted. Clearing a bit position which is set, indicating an
active interrupt, does not clear the interrupt.
HARDWARE REFERENCE
3-31
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