Intel i960 Series User Manual page 6

CONTENTS
TABLES
Table 3-1 External Connectors and LEDs .......................................................................................................... 3-2
Table 3-2 CPU Module Frequency Switch Settings............................................................................................ 3-3
Table 3-3 i960 Jx/Hx CPU Clock Rates .............................................................................................................. 3-4
Table 3-4 DRAM Access Times.......................................................................................................................... 3-6
Table 3-5 DRAM SIMM Configurations .............................................................................................................. 3-7
Table 3-6 Flash ROM Addresses ....................................................................................................................... 3-7
Table 3-7 Interrupt Sources ................................................................................................................................ 3-8
Table 3-8 80960Sx and Kx Interrupt Sources..................................................................................................... 3-8
Table 3-9 80960Sx and Kx Interrupt Switch Settings ......................................................................................... 3-9
Table 3-10 UART Register Addresses ................................................................................................................. 3-9
Table 3-11 Parallel Port Addresses .................................................................................................................... 3-10
Table 3-12 Parallel Port Status Register Bit Assignments.................................................................................. 3-10
Table 3-13 Parallel Port Control Register Bit Assignments ................................................................................ 3-11
Table 3-14 CIO Register Address....................................................................................................................... 3-11
Table 3-15 CIO Port A Bits 5-3 ........................................................................................................................... 3-12
Table 3-16 CIO Port A Bits 2-0 ........................................................................................................................... 3-13
Table 3-17 Available Squall II Modules .............................................................................................................. 3-15
Table 3-18 Squall Module Compatibility at Maximum CPU Clock Speed (33 MHz) ........................................... 3-15
Table 3-19 Local Configuration Registers .......................................................................................................... 3-18
Table 3-20 PCI Configuration Registers ............................................................................................................. 3-19
Table 3-21 Memory Region 0 Settings ............................................................................................................... 3-20
Table 3-22 Local Address Space 0 Range Register........................................................................................... 3-20
Table 3-23 Local Address Space 0 Local Base Address (Re-map) Register Description .................................. 3-20
Table 3-24 Local Bus Region Descriptor for PCI-to-Local Access Register Description .................................... 3-21
Table 3-25 ROM Region Settings ....................................................................................................................... 3-22
Table 3-26 Local Expansion ROM Local Base Address (Re-map) and BREQo Register Description ............... 3-23
Table 3-27 Local Expansion ROM Range Register Description ......................................................................... 3-23
Table 3-28 Local Range Register for Direct Master-to-PCI Description ............................................................. 3-25
Table 3-29 PCI Base Address (Re-map) Register for Direct Master-to-PCI Description .................................... 3-25
Table 3-30 Local Bus Base Address Register for Direct Master-to-PCI Memory ............................................... 3-26
Table 3-31 Local Base Address for Direct Master-to-PCI IO/CFG Register ....................................................... 3-26
Table 3-32 PCI Configuration Address Register for Direct Master-to-PCI IO/CFG ............................................ 3-27
Table 3-33 Interrupt Control/Status .................................................................................................................... 3-29
Table 4-1 DRAM Profiles .................................................................................................................................... 4-8
Table 5-1 Power Supply ..................................................................................................................................... 5-3
Table 5-2 Pin Description Nomenclature ............................................................................................................ 5-5
Table 5-3 Squall Module Signal Descriptions ..................................................................................................... 5-5
Table 5-4 Squall II Module Slave Timing ............................................................................................................ 5-9
Table 5-5 Squall II Module Master Timing ........................................................................................................ 5-13
Table 5-6 Squall II Module Pin Assignments .................................................................................................... 5-17
Table 5-7 Squall II Module Signal Loading ....................................................................................................... 5-18
Table A-1 Cyclone EP/PCI-SDK Platform Bill Of Materials................................................................................. A-1
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