Table 5-4 Squall Ii Module Slave Timing - Intel i960 Series User Manual

Name Minimum
t1 Note
t2 2
t4 10
t5 2
t6 Note
t7 Note
t8 Note
t9 12
t10 0
t11 Note
NOTE:
Signal timing is dependent on the type of i960 processor and the frequency of operation. Refer to Intel i960 pr o-
cessor data sheets for this timing information .
Figure 5-5, Squall II Slave Burst Read Timing Diagram shows 3,1,1,1 clock cycle read; Figure 5-6,
Squall II Slave Burst Write Timing Diagram shows 3,2,2,2 clock cycle write. Any number of wait states
may be run by Squall module slaves.
Table 5-4. Squall II Module Slave Timing
Maximum
Note Clock to Output S_ADS
10 Clock to Output, SQxSEl
-- Read S_DATA Setup to Clock
-- S_DATA hold from Clock
Note Clock to Output, S_BLAST BE[3:0]
Note Clock to Output, S_ADDR [31:02]
Note Clock to Output, S_W/R
-- S_READY Setup to Clock
-- S_READY Hold from Clock
Note Clock to Output, S_DATA (Write)
SQUALL II MODULE INTERFACE
Comment
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