Intel i960 Series User Manual page 93

1 2 3
D612A.TD
PMCLK
t2
SQBR
t1
SQBG
t11
S_ADS
t11
S_BLAST
S_EXTEND
t11
S_ADDR
t11
S_W/R
S_DATA
S_READY
Figure 5-8. Squall II Master Burst Read and Write Timing Diagram
Figure 5-9, Squall II Master Read Using S_EXTEND, shows a three clock cycle access. Refresh cycles
may cause READY to be delayed by up to 10 additional clock cycles.
Read cycle extends by asserting EXTEND. Valid data is placed on the bus by the DRAM when READY
is asserted. Valid data is held on the bus for every rising clock edge in which EXTEND is asserted.
Cycle ends with BLAST and READY asserted and EXTEND negated.
4 5 6 7 8 9
t10
t10
t2
t2
t4 t4
t3 t3
t3
t3
t5
t5
SQUALL II MODULE INTERFACE
10 11 12 13 14 15 16
t8
t7
t5
17 18 19 20 21
t2
t1
t9
t9
t9
t10
t9
t9
5-15