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ERRATA (5/95)
Figure 3-2, DRAM Memory Map for Cyclone EP, incorrectly showed the
PCI Bus Address as 1000 0000H. It now correctly shows 4000 0000H.
CPU Module Flash Boot ROM
for 80960Cx / Jx / Hx
F000 0000H
Expansion Flash ROM
E000 0000H
D000 0000H
C000 0000H
B00C 0000H
B008 0000H
B004 0000H
B000 0000H
A000 0000H
8000 0000H
4000 0000H
CPU Module Flash Boot ROM
0000 0000H
3.4
INTERLEAVED DRAM
The Cyclone EP is initially configured with 2 Mbytes of interleaved DRAM. This memory, located in
the SIMM sockets, is upgradeable to 8 or 32 Mbytes. Figure 3-1 (pg. 3-1) shows the SIMMs and
sockets. Section 3.4.2 discusses the DRAM configuration options.
Access to this DRAM can be shared with the Squall II Module I/O device's DMA controller. A priority
arbitration circuit ensures that only one device is using the memory at a time.
3.4.1
DRAM Performance
The DRAM controller automatically adjusts wait states based on processor type, processor clock
frequency, and memory speed. The controller supports burst transfers using the interleaved banks to
maximize performance. Table 3-4 lists DRAM performance.
The default memory configuration uses 70 ns memory. At processor frequencies of 25 and 40 MHz,
wait states are reduced using 60 ns memory.
Reserved
Squall Module
Reserved
Parallel Port
CIO
Serial Port
DRAM
Reserved
PLX PCI 9060
(PCI - SDK only)
PCI Bus
(PCI - SDK only)
for 80960Kx / Sx
Figure 3-2. DRAM Memory Map for Cyclone EP
HARDWARE REFERENCE
EFFF FFFFH
Expansion Flash ROM
Flash Socket 1 (U27)
E004 0000H
E000 0000H
Flash Socket 2 (U22)
3-5
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