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GE UR Series Instruction Manual Page 285

Line differential relay.
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8 THEORY OF OPERATION
Phase angle deviation computed from currents is used whenever it is valid. Otherwise, phase angle information from
the ping-pong algorithm is used.
Phase angle deviation computed from currents is deemed valid whenever the currents are large enough, and when the
deviation computed from the ping-pong information is below a fixed threshold (this threshold is plus or minus half-
cycle).
A secondary loop is formed through the frequency deviation input of the filter. Whenever frequency deviation information is
available, it is used for this input. Otherwise, the input is zero. Because frequency is the derivative of phase information, the
appropriate filter for frequency deviation is simply an integrator, which is combined with the integrator of the PI filter for the
phase. It is very important to combine these two integrators into a single function because it can be shown if two separate
integrators are used, they can drift in opposite directions into saturation, because the loop would only drive their sum to
zero.
In normal operation, frequency tracking at each terminal matches the tracking at all other terminals, because all terminals
will measure approximately the same frequency deviation. However, if there is not enough current at a terminal to compute
frequency deviation, frequency tracking at that terminal is accomplished indirectly via phase locking to other terminals. A
small phase deviation must be present for the tracking to occur. To keep the deviation from exceeding the target of 0.01
radians, the slew rate of frequency tracking should be limited to about 0.0001 Hz per second. With a worst case step
change of 0.1 Hz, the time constant of frequency tracking should be at least 1000 seconds.
Also shown in the loop is the clock itself, because it behaves like an integrator. The clock is implemented in hardware and
software with a crystal oscillator and a counter.
Because the ratio of the time step of the integrators (1/60 second) to the shortest time constant (10 seconds) is so small (1/
600), integrators can be implemented simply as the simple summations with a gain multiplier of the time step (1/60 sec-
ond).
delta omega
delta phi time
delta phi current
There are 4 gains in the filter that must be selected once and for all as part of the design of the system. The gains are deter-
mined by the time step of the integrators, and the desired time constants of the system as follows:
T
repeat
KI
=
----------------- -
2
T
phase
2
KP
=
---------------- -
T
phase
T
repeat
KF
=
------------------------- -
T
frequency
GE Power Management
+
+
KF
+
KI
SWITCH
KP
Figure 8–6: BLOCK DIAGRAM OF LOOP FILTER
L90 Line Differential Relay
1/(Z–1)
+
omega
+
+
1/(Z–1)
[this is the clock]
phi
8.1 OVERVIEW
8
8-11

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