Reset Initial Conditions - Holtek HT66F488 Manual

HT66F488/HT66F489
A/D Flash MCU with EEPROM
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for
t details.
SST
Note: The t
The t
The t

Reset Initial Conditions

The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO PDF
�
u
1
1
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
P�og�a� Counte�
Inte��upts
WDT
Ti�e� Modules
Input/Output Po�ts
Stack Pointe�
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that
where more than one package type exists the table will reflect the situation for the larger package
type.
Rev. 1.21
W D T T i m e - o u t
I n t e r n a l R e s e t
is 15~16 clock cycles if the system clock source is provided by the HIRC.
SST
is 128 clock cycles for HXT/LXT.
SST
is 1~2 clock cycles for the LIRC.
SST
WDT Time-out Reset during SLEEP or IDLE Timing Chart
� Powe�-on �eset
u LVR �eset du�ing �ORMAL o� SLOW Mode ope�ation
u WDT ti�e-out �eset du�ing �ORMAL o� SLOW Mode ope�ation
1 WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation
Item
Reset to ze�o
All inte��upts will �e disa�led
Clea� afte� �eset� WDT �egins counting
Ti�e� Modules will �e tu�ned off
I/O po�ts will �e setup as inputs
Stack Pointe� will point to the top of the stack
51
t
S S T
RESET Conditions
�ote: "u" stands fo� unchanged
Condition After RESET
�ove��e� ��� 2�1�