Fast Wake-Up - Holtek HT66F488 Manual

IDLEN: IDLE Mode Control
Bit 1
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0 HLCLK: System Clock Selection
0: f
1: f
This bit is used to select if the f
system clock. When the bit is high the f
f /64 or f
H
f clock and the f
L
CTRL Register
Bit 7
�a�e FSYSO�
R/W R/W
POR �
Bit 7 FSYSON: f
0: Disable
1: Enable
Bit 6~ 3 Unimplemented, read as "0"
Bit 2 LVRF: LVR function reset flag
Describe elsewhere
Bit 1 LRF: LVRC register software reset flag
Describe elsewhere
Bit 0 WRF: WDTC register software reset flag
Describe elsewhere

Fast Wake-up

To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system
clock source to the device will be stopped. However when the device is woken up again, it can take
a considerable time for the original system oscillator to restart, stabilise and allow normal operation
to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is
provided, which allows f
system oscillator has stabilised. The temporary clock is sourced by the LIRC or LXT oscillator. As
the clock source for the Fast Wake-up function is f
in the SLEEP and IDLE0 modes. The Fast Wake-up enable/disable function is controlled using the
FSTEN bit in the SMOD register.
If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up
function is enabled, then it will take one to two t
system will then initially run under the f
at which point the HTO flag will switch high and the system will switch over to operating from the
HXT oscillator.
Rev. 1.21
/2 ~ f /64 or f
H H L
H
clock or the f
H
clock will be selected. When system clock switches from the f
L
clock will be automatically switched off to conserve power.
H
6 5 4
— — —
— — —
— — —
Control IDLE Mode
SYS
, to act as a temporary clock to first drive the system until the original
SUB
clock source until 128 HXT clock cycles have elapsed,
SUB
42
HT66F488/HT66F489
A/D Flash MCU with EEPROM
/2 ~ f /64 or f clock is used as the
H H L
clock will be selected and if low the f
H
3 2
— LVRF LRF
— R/W R/W
— �
, the Fast Wake-up function is only available
SUB
clock cycles for the system to wake-up. The
SUB
�ove��e� ��� 2�1�
/2 ~
H
clock to the
H
1 0
WRF
R/W
� �