Holtek HT66F488 Manual page 166

1
C O M 0
C O M 1 0
C O M 2
0
0
C O M 3
S E G 0
0
S E G 1
1
A cyclic LCD waveform includes two frames, known as Frame 0 and Frame 1 which is selected by
the FRAME bit in the SLCDC0 register. The following offers a functional explanation.
To select Frame 0 clear the FRAME bit to 0.
In frame 0, the COM signal output can have a value of V
The SEG signal can have a value of V
In frame 1, the COM signal output can have a value of V
The SEG signal can have a value of V
The SCOM0~SCOMn waveform is controlled by the application program using the FRAME bit,
and the corresponding I/O data register for the respective SCOM pin to determine whether the
SCOM0~SCOMn output has a value of either V
is controlled in a similar way using the FRAME bit and the corresponding I/O data register for the
respective SSEG pin to determine whether the SSEG0~SSEGn output has a value of either V
or Vbias.
Rev. 1.21
A/D Flash MCU with EEPROM
f r a m e 0
0
0 0 0 1
0 0 0
1 1
0 0 0
0
1
0 0 0 0
1
0 1 1 0 0
1 1 0 1 1
1/3 Bias LCD Waveform
, or have a Vbias value of 2/3V
SS
have a Vbias value of 1/3V
DD
, V
DD
166
HT66F488/HT66F489
f r a m e 0
f r a m e 1
0 0
1
0 0 0
1
0
1
0 0
0 0 0
1
1 1 0 0
1 0 1 0
, or have a Vbias value of 1/3V
DD
(SEG_H).
DD
, or have a Vbias value of 2/3V
SS
(SEG_L).
DD
or Vbias. The SSEG0~SSEGm waveform
SS
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V D D
2 / 3 V D D
1 / 3 V D D
V S S
V D D
2 / 3 V D D
1 / 3 V D D
V S S
V D D
2 / 3 V D D
1 / 3 V D D
V S S
V D D
2 / 3 V D D
1 / 3 V D D
V S S
V D D
2 / 3 V D D
1 / 3 V D D
V S S
V D D
2 / 3 V D D
1 / 3 V D D
V S S
(SEG_L).
DD
(SEG_H).
DD
, V
DD SS