Holtek HT66F488 Manual page 134

RXIF: Receive RXR data register status
Bit 2
0: RXR data register is empty
1: RXR data register has available data
The RXIF flag is the receive data register status flag. When this read only flag is "0",
it indicates that the RXR read data register is empty. When the flag is "1", it indicates
that the RXR read data register contains new data. When the contents of the shift
register are transferred to the RXR register, an interrupt is generated if RIE=1 in the
UCR2 register. If one or more errors are detected in the received word, the appropriate
receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The
RXIF flag is cleared when the USR register is read with RXIF set, followed by a read
from the RXR register, and if the RXR register has no data available.
Bit 1 TIDLE: Transmission idle
0: Data transmission is in progress (data being transmitted)
1: No data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only
flag is "0", it indicates that a transmission is in progress. This flag will be set to "1"
when the TXIF flag is "1" and when there is no transmit data or break character being
transmitted. When TIDLE is equal to "1", the TX pin becomes idle with the pin state
in logic high condition. The TIDLE flag is cleared by reading the USR register with
TIDLE set and then writing to the TXR register. The flag is not generated when a data
character or a break is queued and ready to be sent.
Bit 0 TXIF: Transmit TXR data register status
0: Character is not transferred to the transmit shift register
1: Character has transferred to the transmit shift register (TXR data register is
The TXIF flag is the transmit data register empty flag. When this read only flag is "0",
it indicates that the character is not transferred to the transmitter shift register. When
the flag is "1", it indicates that the transmitter shift register has received a character
from the TXR data register. The TXIF flag is cleared by reading the UART status
register (USR) with TXIF set and then writing to the TXR data register. Note that
when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data
register is not yet full.
UCR1 register
The UCR1 register together with the UCR2 register are the two UART control registers that are used
to set the various options for the UART function, such as overall on/off control, parity control, data
transfer bit length etc. Further explanation on each of the bits is given below:
Bit 7
�a�e UARTE�
R/W R/W
POR �
Bit 7 UARTEN: UART function enable control
0: Disable UART. TX and RX pins are as I/O or other pin-shared functional pins
1: Enable UART. TX and RX pins function as UART pins
The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART
will be disabled and the RX pin as well as the TX pin will be as General Purpose I/O
or other pin-shared functional pins. When the bit is equal to "1", the UART will be
enabled and the TX and RX pins will function as defined by the TXEN and RXEN
enable control bits.
Rev. 1.21
empty)
6 5
B�O PRE� PRT
R/W R/W R/W
� �
134
HT66F488/HT66F489
A/D Flash MCU with EEPROM
4 3 2
STOPS TXBRK
R/W R/W
� � �
�ove��e� ��� 2�1�
1 0
RX8 TX8
R W
x �
"x" unknown