HT66F488/HT66F489
A/D Flash MCU with EEPROM
TBC Register
Bit
7
�a�e
TBO�
R/W
R/W
POR
�
TBON: TB0 and TB1 Control bit
Bit 7
0: Disable
1: Enable
TBCK: Select f
Bit 6
0: f
1: f
TB11 ~ TB10: Select Time Base 1 Time-out Period
Bit 5 ~ 4
00: 4096/f
01: 8192/f
10: 16384/f
11: 32768/f
LXTLP: LXT Low Power Mode control
Bit 3
0: Disable (Quick Start Mode)
1: Enable (Low Power Mode)
Bit 2 ~ 0
TB02 ~ TB00: Select Time Base 0 Time-out Period
000: 2
001: 2
010: 2
011: 2
100: 2
101: 2
110: 2
111: 2
LXT
LIRC
Serial Interface Module Interrupts
A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which
occurs when a byte of data has been received or transmitted by the SIM interface. To allow the
program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI,
and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled,
the stack is not full and a byte of data has been transmitted or received by the SIM interface, a
subroutine call to the respective Interrupt vector, will take place. When the interrupt is serviced, the
respective interrupt request flag, SIMF, will be automatically reset and the EMI bit will be cleared to
disable other interrupts.
Rev. 1.21
6
5
4
TBCK
TB11
TB1�
R/W
R/W
R/W
�
1
1
Clock
TB
TBC
/4
SYS
TB
TB
TB
TB
/f
8
TB
/f
9
TB
/f
10
TB
/f
11
TB
/f
12
TB
/f
13
TB
/f
14
TB
/f
15
TB
f
/4
SYS
M
f
M
TB
U
U
X
f
X
TBC
TBCK bit
Configuration
Option
Time Base Interrupt
15�
3
2
1
LXTLP
TB�2
TB�1
R/W
R/W
R/W
�
1
1
TB02~TB00
8
15
÷2
~2
Time Base 0 Interrupt
12
15
÷2
~2
Time Base 1 Interrupt
TB11~TB10
�ove��e� ��� 2�1�
0
TB��
R/W
1
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