Holtek HT66F488 Manual page 100

Single Pulse Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10
respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the PTnON
bit can also be made to automatically change from low to high using the external PTCKn pin,
which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The PTnON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the PTnON bit is cleared to zero, which can be implemented using the application program or
when a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PTnON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter
can only be reset back to zero when the PTnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR bit is not used in this Mode.
S / W C o m m a n d
S E T " P T n O N "
P T C K n P i n T r a n s t i o n
P T M n O u t p u t P i n
Rev. 1.21
L e a d i n g E d g e
P T n O N b i t
o r
0 ® 1
P u l s e W i d t h = C C R A V a l u e
Single Pulse Generation (n=0, 1)
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HT66F488/HT66F489
A/D Flash MCU with EEPROM
T r a i l i n g E d g e
S / W C o m m a n d
C L R " P T n O N "
P T n O N b i t
o r
1 ® 0
C C R A M a t c h C o m p a r e
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