Reset Initial Conditions - Holtek TinyPower HT69F40A Manual

TinyPower
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for
t details.
SST
Note: The t
HIRC. The t

Reset Initial Conditions

The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
0
u
1
1
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
P�og�am Counte�
Inte��upts
WDT� Time Base
Time� Modules
Input/�utput Po�ts
Sta�k Pointe�
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects the microcontroller internal registers.
Rev. 1.20
HT69F30A/HT69F40A/HT69F50A
I/O Flash 8-Bit MCU with LCD & EEPROM
TM
W D T T i m e - o u t
I n t e r n a l R e s e t
WDT Time-out Reset during SLEEP or IDLE Timing Chart
is 15~16 clock cycles if the system clock source is provided by ERC or
SST
is 1024 clock for HXT or LXT. The t
SST
PDF
0 Powe�-on �eset
u RES o� LVR �eset du�ing N�RMAL o� SL�W Mode ope�ation
u WDT time-out �eset du�ing N�RMAL o� SL�W Mode ope�ation
1 WDT time-out �eset du�ing IDLE o� SLEEP Mode ope�ation
Item Condition After RESET
Reset to ze�o
All inte��upts will �e disa�led
Clea� afte� �eset� WDT �egins �ounting
Time� Modules will �e tu�ned off
I/� po�ts will �e setup as inputs
Sta�k Pointe� will point to the top of the sta�k
74
t
S S T
is 1~2 clock for LIRC.
SST
RESET Conditions
"u" stands for unchanged
��to�e� 0�� 201�