Holtek HT66F488 Manual page 91

HT66F488/HT66F489
A/D Flash MCU with EEPROM
PTM register description
Overall operation of the P-type TM is controlled using a series of registers. A read only register pair
exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the
internal 10-bit CCRA/CCRP value. The remaining two registers are control registers which setup the
different operating and control modes.
Register
Name
PTMnC� PTnPAU
PTMnC1 PTnM1
PTMnDL
PTMnDH
PTMnAL
PTMnAH
PTMnRPL
PTMnRPH
PTMnC0 Register
Bit 7
�a�e PTnPAU
R/W R/W
POR �
PTnPAU: PTMn Counter Pause Control
Bit 7
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6 ~4 PTnCK2 ~ PTnCK0: Select PTMn Counter clock
000: f
001: f
010: f
011: f
100: f
101: f
110: PTCKn rising edge clock
111: PTCKn falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source f
the system clock, while f
be found in the oscillator section.
Rev. 1.21
7 6 5
PTnCK2 PTnCK1 PTnCK�
PTnM� PTnIO1 PTnIO�
D� D6 D5
— — —
D� D6 D5
— — —
D� D6 D5
— — —
10-bit Periodic TM Register List (n=0, 1)
6 5
PTnCK2 PTnCK1 PTnCK�
R/W R/W
� �
/4
SYS
SYS
/16
H
/64
H
TBC
TBC
and f
H TBC
�1
Bit
4 3 2
PTnO� —
PTnOC PTnPOL PTnCKS PTnCCLR
D4 D3 D2
— — —
D4 D3 D2
— — —
D4 D3 D2
— — —
4 3 2
PTnO� —
R/W R/W —
� � —
are other internal clocks, the details of which can
1 0
— —
D1 D�
D� D8
D1 D�
D� D8
D1 D�
D� D8
1 0
— —
— —
— —
is
SYS
�ove��e� ��� 2�1�