Reset Initial Conditions - Holtek BS83A04C Manual

• RSTFC Register
Bit 7
Name —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
RSTF: Reset control register software reset flag
Bit 3
Describe elsewhere.
Bit 2 LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1 Unimplemented, read as "0"
WRF: WDT control register software reset flag
Bit 0
Describe elsewhere.
Watchdog Time-out Reset during Normal Operation
When a Watchdog time-out Reset during normal operations in the FAST or SLOW mode, the
Watchdog time-out flag TO will be set to "1".
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the System Start Up Time
Characteristics for t

Reset Initial Conditions

The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
Rev. 1.00
4-Key Enhanced Touch I/O Flash MCU
6 5 4
— — —
— — —
— — —
WDT Time-out
Internal Reset
WDT Time-out Reset during Normal Operation Timing Chart
details.
SST
WDT Time-out
Internal Reset
WDT Time-out Reset during SLEEP or IDLE Timing Chart
44
BS83A04C
3 2 1
RSTF LVRF —
R/W R/W —
0 x —
t
RSTD
t
SST
0
WRF
R/W
0
"x": unknown
March 24, 2020