Holtek HT66F488 Manual page 32

EED Register
Bit 7
�a�e D�
R/W R/W
POR �
D7~D0: Data EEPROM data
Bit 7~0
Data EEPROM data bit 7 ~ bit 0
EEC Register
Bit 7
�a�e —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
Bit 3 WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2 WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
RDEN: Data EEPROM Read Enable
Bit 1
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0 RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The
WR and RD can not be set to "1" at the same time.
Rev. 1.21
A/D Flash MCU with EEPROM
6 5 4
D6 D5 D4
R/W R/W R/W
� � �
6 5 4
— — —
— — —
— — —
32
HT66F488/HT66F489
3 2 1
D3 D2 D1
R/W R/W R/W
� � �
3 2 1
WRE� WR RDE�
R/W R/W R/W
� � �
�ove��e� ��� 2�1�
0
D�
R/W
�
0
RD
R/W
�