Holtek HT66F488 Manual page 108

ACERL Register
Bit 7
�a�e ACE�
R/W R/W
POR 1
ACE7: Define PB1 is A/D input or not
Bit 7
0: Not A/D input
1: A/D input, AN7
ACE6: Define PC6 is A/D input or not
Bit 6
0: Not A/D input
1: A/D input, AN6
ACE5: Define PC5 is A/D input or not
Bit 5
0: Not A/D input
1: A/D input, AN5
ACE4: Define PC4 is A/D input or not
Bit 4
0: Not A/D input
1: A/D input, AN4
ACE3: Define PC3 is A/D input or not
Bit 3
0: Not A/D input
1: A/D input, AN3
ACE2: Define PC0 is A/D input or not
Bit 2
0: Not A/D input
1: A/D input, AN2
Bit 1 ACE1: Define PB7 is A/D input or not
0: Not A/D input
1: A/D input, AN1
Bit 0 ACE0: Define PB6 is A/D input or not
0: Not A/D input
1: A/D input, AN0
A/D Operation
The START bit in the ADCR0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset.
It is the START bit that is used to control the overall start operation of the internal analog to digital
converter.
The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to "0" by the microcontroller after a
conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set
in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock f
to be either f or a subdivided version of f
SYS
ADCK2~ADCK0 bits in the ADCR1 register.
Rev. 1.21
A/D Flash MCU with EEPROM
6 5 4
ACE6 ACE5 ACE4
R/W R/W R/W
1 1 1
. The division ratio value is determined by the
SYS
1�8
HT66F488/HT66F489
3 2 1
ACE3 ACE2 ACE1
R/W R/W R/W
1 1 1
, can be chosen
SYS
�ove��e� ��� 2�1�
0
ACE�
R/W
1