Counter
Value
CCRP
CCRA
STON
STPAU
STPOL
CCRA Int.
Flag STMAF
CCRP Int.
Flag STMPF
STM O/P Pin
(STOC=1)
STM O/P Pin
(STOC=0)
PWM Duty Cycle
set by CCRA
Note: 1. Here STDPX = 0 - Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues running even when STIO[1:0] = 00 or 01
4. The STCCLR bit has no influence on PWM operation
Rev. 1.21
Counter Cleared by CCRP
Pause
PWM Period
set by CCRP
PWM Mode – STDPX=0
84
HT66F488/HT66F489
A/D Flash MCU with EEPROM
STDPX=0;STM[1:0]=10
Counter reset when
STON returns high
Counter Stop If
Resume
STON bit low
Output Inverts
PWM resumes
Output controlled by
operation
Other pin-shared function
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Time
When STPOL = 1
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