Holtek HT66F488 Manual page 141

HT66F488/HT66F489
A/D Flash MCU with EEPROM
Transmitting data
When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with
the least significant bit first. In the transmit mode, the TXR register forms a buffer between the
internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been
selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a
data transfer can be summarized as follows:
• Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word
length, parity type and number of stop bits.
• Setup the BRG register to select the desired baud rate.
• Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin.
• Access the USR register and write the data that is to be transmitted into the TXR register. Note
that this step will clear the TXIF bit.
• This sequence of events can now be repeated to send additional data.
It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register.
Clearing the TXIF flag is always achieved using the following software sequence:
1. A USR register access
2. A TXR register write execution
The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is
empty and that other data can now be written into the TXR register without overwriting the previous
data. If the TEIE bit is set then the TXIF flag will generate an interrupt.
During a data transmission, a write instruction to the TXR register will place the data into the TXR
register, which will be copied to the shift register at the end of the present transmission. When there
is no data transmission in progress, a write instruction to the TXR register will place the data directly
into the shift register, resulting in the commencement of data transmission, and the TXIF bit being
immediately set. When a frame transmission is complete, which happens after stop bits are sent
or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software
sequence is used:
1. A USR register access
2. A TXR register write execution
Note that both the TXIF and TIDLE bits are cleared by the same software sequence.
Transmit break
If the TXBRK bit is set then break characters will be sent on the next transmission. Break character
transmission consists of a start bit, followed by 13×N '0' bits and stop bits, where N=1, 2, etc. If a
break character is to be transmitted then the TXBRK bit must be first set by the application program,
then cleared to generate the stop bits. Transmitting a break character will not generate a transmit
interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually
kept at a logic high level then the transmitter circuitry will transmit continuous break characters.
After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the
last break character and subsequently send out one or two stop bits. The automatic logic highs at the
end of the last break character will ensure that the start bit of the next frame is recognized.
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