Watchdog Ti�E� Ope�Ation - Holtek HT66F488 Manual

Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear WDT instructions will not be executed
in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With
regard to the Watchdog Timer enable/reset function, there are five bits, WE4~WE0, in the WDTC
register to additional enable and reset control of the Watchdog Timer.
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a value other than 01010B and 10101B is written into the
WE4~WE0 bit locations, the second is using the Watchdog Timer software clear instructions and the
third is via a HALT instruction. There is only one method of using software instruction to clear the
Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT.
The maximum time-out period is when the 2
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
seconds for the 2
18
WDTC Register
"CLR WDT"Instruction
Rev. 1.21
WE4 ~ WE0 Bits
1�1�1B/�1�1�B
Any othe� value
Watchdog Timer Enable/Reset Control
division ratio is selected. As an example, with a 32
18
division ratio, and a minimum timeout of 7.8ms for the 2
WE4~WE0 bits
M
LXT
f
SUB
U 8-stage Divider
LIRC
X
Configuration option WS2~WS0
8
(f /2 ~ f
SUB
Watchdog Timer
48
HT66F488/HT66F489
A/D Flash MCU with EEPROM
WDT Function
Ena�le
Reset MCU
division ration.
8
Reset MCU
CLR
8
f /2
SUB
WDT Prescaler
8-to-1 MUX WDT Time-out
18 8
/2 ) (2 /f
SUB
�ove��e� ��� 2�1�
18
~ 2 /f )
SUB SUB