Cont�Ol Registe - Holtek HT66F488 Manual

HT66F488/HT66F489
A/D Flash MCU with EEPROM
IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the
system oscillator will be inhibited from driving the CPU but may continue to provide a clock source
to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1
Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low
speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, f
Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
SMOD Register
Bit 7
�a�e CKS2
R/W R/W
POR �
CKS2 ~ CKS0: The system clock selection bits when HLCLK=0
Bit 7 ~ 5
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be the LIRC or LXT, a divided version
of the high speed system oscillator can also be chosen as the system clock source.
Bit 4 FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the f
initially used after the device wakes up. When the bit is high, the f
be used as a temporary system clock to provide a faster wake up time as the f
is available.
Bit 3 LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset.
Bit 2 HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to "0" by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as "1" by the application program after
device power-on. The flag will be low when in the SLEEP, IDLE0 or SLOW0 Mode,
but after power on reset or a wake-up has occurred, the flag will change to a high level
after 128 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the
HIRC oscillator is used.
Rev. 1.21
6 5 4
CKS1 CKS� FSTE�
R/W R/W R/W
� � �
(LIRC or LXT)
L
(LIRC or LXT)
L
/64
H
/32
H
/16
H
/8
H
/4
H
/2
H
41
, will be on.
SUB
3 2 1
LTO HTO IDLE�
R R R/W
� � 1
clock source is
SUB
clock source can
SUB
�ove��e� ��� 2�1�
0
HLCLK
R/W
1
clock
SUB