Holtek HT66F488 Manual page 47

HT66F488/HT66F489
A/D Flash MCU with EEPROM
WDTC Register
Bit 7
�a�e WE4
R/W R/W
POR �
WE4 ~ WE0: WDT function software control
Bit 7~ 3
10101/01010: WDT enable
Other values: Reset MCU
When these bits are changed to any other values by the environmental noise to reset
the microcontroller, the reset operation will be activated after 2~3 t
and the WRF bit in the CTRL register will be set to 1to indicate the reset source.
Bit 2~ 0 WS2 ~ WS0: WDT Time-out period selection
000: 2
001: 2
010: 2
011: 2
100: 2
101: 2
110: 2
111: 2
These three bits determine the division ratio of the Watchdog Timer sourece clock,
which in turn determines the timeout period.
CTRL Register
Bit 7
�a�e FSYSO�
R/W R/W
POR �
FSYSON: f
Bit 7
Describe elsewhere
Bit 6~ 3 Unimplemented, read as "0"
Bit 2 LVRF: LVR function reset flag
Describe elsewhere
Bit 1 LRF: LVRC register software reset flag
Describe elsewhere
Bit 0 WRF: WDTC register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDTC Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Rev. 1.21
6 5 4
WE3 WE2 WE1
R/W R/W R/W
1 � 1
/f
8
SUB
/f
10
SUB
/f
12
SUB
/f
14
SUB
/f
15
SUB
/f
16
SUB
/f
17
SUB
/f
18
SUB
6 5 4
— — —
— — —
— — —
Control IDLE Mode
SYS
4�
3 2 1
WE� WS2 WS1
R/W R/W R/W
� � 1
clock cycles
SUB
3 2 1
— LVRF LRF
— R/W R/W
— � �
�ove��e� ��� 2�1�
0
WS�
R/W
1
0
WRF
R/W
�