HT66F488/HT66F489
A/D Flash MCU with EEPROM
Mnemonic
Branch
LSZ [�]
Skip if Data Me�o�y is ze�o
LSZA [�]
Skip if Data Me�o�y is ze�o with data �ove�ent to ACC
LS�Z [�]
Skip if Data Me�o�y is not ze�o
LSZ [�].i
Skip if �it i of Data Me�o�y is ze�o
LS�Z [�].i
Skip if �it i of Data Me�o�y is not ze�o
LSIZ [�]
Skip if inc�e�ent Data Me�o�y is ze�o
LSDZ [�]
Skip if dec�e�ent Data Me�o�y is ze�o
LSIZA [�]
Skip if inc�e�ent Data Me�o�y is ze�o with �esult in ACC
LSDZA [�]
Skip if dec�e�ent Data Me�o�y is ze�o with �esult in ACC
Table Read
LTABRD [�]
Read ta�le to TBLH and Data Me�o�y
LTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y
LITABRD [�] Increment table pointer TBLP first and Read table to TBLH and Data Memory
Increment table pointer TBLP first and Read table (last page) to TBLH and
LITABRDL [�]
Data Me�o�y
Miscellaneous
LCLR [�]
Clea� Data Me�o�y
LSET [�]
Set Data Me�o�y
LSWAP [�]
Swap ni��les of Data Me�o�y
LSWAPA [�]
Swap ni��les of Data Me�o�y with �esult in ACC
Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles
are required, if no skip takes place two cycles is required.
2. Any extended instruction which changes the contents of the PCL register will also require three cycles for
execution.
Rev. 1.21
Description
1�5
Cycles Flag Affected
2
�ote
�one
2
�ote
�one
2
�ote
�one
2
�ote
�one
2
�ote
�one
2
�ote
�one
2
�ote
�one
2
�ote
�one
2
�ote
�one
3
�ote
�one
3
�ote
�one
3
�ote
�one
3
�ote
�one
2
�ote
�one
2
�ote
�one
2
�ote
�one
2
�one
�ove��e� ��� 2�1�
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