Table of Contents
Advertisement
S1R72104 Technical Manual
7.3.3 SCSI Interrupt Status 2 (SCSIINT2) R/W
Shows the result of a SCSI control command executed.
The CPU can recognize the interrupt source by reading this register after receiving the interrupt signal. It
clears the bit by writing again the value read.
7
6
5
-
SRST
OFERR
BIT7 RESERVED
BIT6 SCSI RST ASSERTION DETECTED
This bit becomes HIGH if SCSI RST was asserted.
BIT5 OFFSET ERROR IN SYNCHRONOUS TRANSFER
This bit becomes HIGH if an off-set error occurred during synchronous transfer. The off-set error means that the
off-set counter is not reset to "0" when transfer ends, or that the counter overflows/underflows.
BIT4 UNDEFIND GROUP COMMAND
This bit becomes HIGH if SCSI command other than group 0, 1, 2, or 5 was received.
BIT3 COMMAND ERROR
This bit becomes HIGH if an undefined SCSI control command was issued or a control command was issued during
execution of another command.
BIT2 RESELECTED
This bit becomes HIGH if any other device made re-selection during execution of a command other than the SCSI
control command which makes re-selection.
BIT1 SELECTED
This bit becomes HIGH if any other device made selection during execution of a command other than SCSI control
command which makes selection.
BIT0 LOST ARBITRATION
This bit becomes HIGH in the case of defeat in the arbitration phase. If this bit is HIGH and no other device made
selection or re-selection , the IC suspends the operation of the control commands.
7.3.4 Reset (RESET) W
Writing in this register initializes the inside of the circuit. Any value may be entered.
7
6
5
MSB
12
4
3
2
UNDEF
CMDER
RESEL
4
3
2
1
0
02h
SEL
LARBT
LOST ARBITRATION
SELECTED
RESELECTED
COMMAND ERROR
UNDEFIND GROUP COMMAND
OFFSET ERROR IN SYNCHRONOUS TRANSFER
SCSI RST ASSERTION DETECTED
1
0
07h
LSB
EPSON
Rev.1.1
Advertisement
Table of Contents
