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Functional Description
2.5
Watchdog Timer
The CP3002 provides a Watchdog timer that is programmable for a timeout period ranging from
125 ms to 4096 s in 16 steps. Failure to trigger the Watchdog timer in time results in a system
reset or an interrupt. In dual-stage mode, a combination of both interrupt and reset if the Watch-
dog is not serviced. A hardware status flag will be provided to determine if the Watchdog timer
generated the reset.
2.6
Battery
The CP3002 is provided with a 3.0 V "coin cell" lithium battery for the RTC. For further informa-
tion concerning the battery and its replacement, refer to Chapter 3.5.7, Battery Replacement.
Note ...
If an 8HP expansion module is used on the CP3002, either the CP3002 or the
expansion module may be equipped with a battery.
Using one battery on the CP3002 and one on the expansion module simulta-
neously may result in premature discharge of the batteries.
2.7
Reset
The CP3002 is automatically reset by a precision voltage monitoring circuit that detects a drop
in voltage below the acceptable operating limit of 4.7 V for the 5 V line and below 3.1 V for the
3.3 V line, or in the event of a power failure of the DC/DC converters. Other reset sources in-
clude the Watchdog timer and the push-button switch on the 8HP front panel. The CP3002 re-
sponds to any of these sources by initializing local peripherals.
A reset will be generated if one the following events occurs:
• +5 V supply falls below 4.7 V typical; level-sensitive
• +3.3 V supply falls below 3.1 V typical; level-sensitive
• Power failure of at least one onboard DC/DC converter; level-sensitive
• Push-button "RESET" pressed (only on CP3002-HDD); edge-sensitive
• Watchdog expired; edge-sensitive
• CompactPCI backplane PRST# input (CompactPCI connector J2, pin C17); edge-sensi-
tive
• CompactPCI backplane RST# input (software configurable when the board is in periph-
eral mode); edge-sensitive
2.8
Flash Memory
The CP3002 provides flash interfaces for redundant uEFI BIOS and the SATA Flash module.
2.8.1
SPI Boot Flash for uEFI BIOS
The CP3002 provides two SPI boot flash chips (2 x 8 MB) for two separate uEFI BIOS images,
a standard SPI boot flash and a recovery SPI boot flash. The configuration for the uEFI BIOS
recovery can be controlled via the DIP switch SW1, switch 2.
The SPI boot flash includes a hardware write protection option, which can be configured via the
uEFI BIOS. If write protection is enabled, the SPI boot flash cannot be written to.
Page 2 - 6
CP3002
ID 1042-9252, Rev. 2.0
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