Renesas HD49335HNP Specification Sheet page 8

Cds/pga & 10-bit a/d tg converter
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HD49335NP/HNP
6. ADC Digital Output Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.
Table 3
ADC Digital Output Functions
H
X
X
X
X
L
L
L
L
L
L
H
H
L
H
H
X
X
H
L
L
L
H
H
L
H
H
X
X
H
X
L
L
L
H
H
L
H
H
Note: 1. STBY, TEST, LINV, and MINV are set by register.
Table 4
ADC Output Code (Binary)
Output Pin
Output
Steps
3
codes
4
5
6
511
512
1020
1021
1022
1023
Table 5
ADC Output Code (Gray)
Output Pin
Output
Steps
3
codes
4
5
6
511
512
1020
1021
1022
1023
Rev.1.0, Feb.12.2004, page 8 of 29
ADC Digital Output
D9
D8
D7
X
Hi-Z
L
Same as in table 4.
L
D9 is inverted in table 4.
L
D8 to D0 are inverted in table 4.
L
D9 to D0 are inverted in table 4.
H
Output code is set up to Clamp Level.
L
Same as in table 5.
L
D9 is inverted in table 5.
L
D8 to D0 are inverted in table 5.
L
D9 to D0 are inverted in table 5.
H
Output code is set up to Clamp Level.
X
H
L
X
L
L
X
H
H
X
L
H
D9
D8
L
L
L
L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
D9
D8
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
H
L
D6
D5
D4
D3
D2
H
L
H
L
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
D7
D6
D5
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
D7
D6
D5
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D1
D0
Operating Mode
Low-power wait state
Normal operation
Pre-blanking
Normal operation
Pre-blanking
L
H
L
Test mode
L
H
L
H
L
H
H
L
H
D4
D3
D2
D1
L
L
L
H
L
L
H
L
L
L
H
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
D4
D3
D2
D1
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
D0
H
L
H
L
H
L
L
H
L
H
D0
L
L
H
H
L
L
L
H
H
L

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