Renesas HD49335HNP Specification Sheet page 22

HD49335NP/HNP
• Address H'F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address
H'F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.
Divided mode
D0 to D7 of address H'F5
D0 to D14 of address H'F8
• Phase settings of high speed pulse (address H'F5 to H'F8)
(1) Select the 1/4 phase from figure 13 at 2 divided mode (D15 = 0 of address H'F8).
Select the 1/6 phase from figure 14 at 3 divided mode (D15 = 1 of address H'F8).
·····P_SP1, P_SP2, P_ADCLK, P_RG
(2) Then select the necessary delay time from figure 15.
·····DL_SP1, DL_SP2, DL_RG, DL_ADCLK
RG can be set both of rising / falling edge optionally.
H1
P_SP1
P_SP2
Figure 13 2 Divided Mode, 1/4 Phase Select (Valid at D15 = 0 of address H'F8)
H1
P_SP1
P_SP2
Figure 14 3 Divided Mode, 1/6 Phase Select (Valid at D15 = 1 of address H'F8)
Default Value of Each Phases
P_SP1
2 divided mode 1
3 divided mode 0
Note: 50% of duty pulse makes tr, tf of RG by DLL.
Address
1 1 1 1 0
Address
1 1 1 1 0
Rev.1.0, Feb.12.2004, page 22 of 29
D15 of address H'F8 = 0
2 divided, 1/4 phase select
Valid
Invalid
Data = 0
Data = 1
Data = 2
Data = 3
Data = 5
Data = 0
Data = 1
Data = 2
Data = 3
Data = 4
P_SP2
2
3
STD1[7:0] (L)
1 1 0 D7 D6 D5
DL_SP2
STD1[7:0] (L)
1 1 1 D7 D6 D5
DL_RG_f
D15 of address H'F8 = 1
3 divided, 1/6 phase select
Invalid
Valid
H1
P_ADCLK
P_RG
H1
P_ADCLK
P_RG
P_ADCLK
1
1
D4 D3 D2 D1 D0
DL_SP1
D4 D3 D2 D1 D0
DL_RG_r
Data = 0
Data = 1
Data = 2
Data = 3
Data = 0
Data = 1
Data = 2
Data = 3
Data = 4
Data = 5
P_RG
0
5
STD2[15:8] (H)
D12 D11 D10 D9 D8
CDS_test DL_ADCLK
STD2[15:8] (H)
D12 D11 D10 D9 D8
Dummy Dummy
clamp th clamp current