Renesas HD49335HNP Specification Sheet page 17

HD49335NP/HNP
Serial Interface Specifications
Timing Specifications
t
INT1
Latches SDATA
at SCK rising edge
CS
SCK
t
su
SDATA
D8 D9
STD2(Upper data)
Item Min Max
f — 5 MHz
SCK
t 50 ns —
INT1,2
t 50 ns —
su
t 50 ns —
ho
The Kind of Data
Data address has 256 type. H'00 to H'FF
H'00
:
Data at timing generator part
:
H'EF
H'F0
:
Data at CDS part
:
H'FF
Address map of each data referred to other sheet.
Details of timing generator refer to the timing chart on the other sheet together with this specification.
This specification only explains about the data of CDS part.
Rev.1.0, Feb.12.2004, page 17 of 29
f
SCK
t
ho
D10 D11 D12 D13 D14 D15 D0 D1
STD1(Lower data)
Figure 8 Serial Interface Timing Specifications
Notes: 1. 3 byte continuous communications.
2. Input SCK with 24 clock when CS is Low.
3. It becomes invalid when data communications are stopped on the way.
4. Data becomes a default with hardware reset.
5. Input more than double frequency of SCK to the CLK_in when transfer
the serial data.
D2 D3 D4 D5 D6 D7 D0 D1
address(address)
Data is determined
at CS rising edge
t
INT2
D2 D3 D4 D5 D6 D7