Renesas HD49335HNP Specification Sheet page 20

HD49335NP/HNP
Address
1 1 1 1 0
• MON (D0 to D2 of address H'F4)
Select the pulse which output to pin MON (pin 60).
When D0 to D2: 0, Fix to Low
When 2, SP1
When 4, OBP
When 6, CPDM
• H12Baff (D3 to D6 of address H'F4)
Select the buffer size which output to pin H1A, H2A (pin 22, 26).
D3: 2 mA buffer
D4: 4 mA buffer
D5: 10 mA buffer
D6: 14 mA buffer
Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer)
• VD latch (D7 of address H'F4)
Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD falling
Differential Code and Gray Code (D8 to D12 of address H'F4)
• Gray code (D8 to D9 of address H'F4)
DC output code can be change to following type.
Gray Code [1] Gray Code [0]
0 0
0 1
1 0
1 1
• Serial data setting items (D10 to D12 of address H'F4)
Setting Bit Setting Contents
Gray_test[0] Standard data output timing control signal
(Refer to the following table)
Gray_test[1]
Gray_test[2] ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
• Standard data output timing
Gray_test[1] Gray_test[0]
Low Low
Low High
High Low
High High
Rev.1.0, Feb.12.2004, page 20 of 29
STD1[7:0] (L)
1 0 0 D7 D6 D5
VD latch H12_Buff
When 1, ADCLK
When 3, SP2
When 5, PBLK
When 7, DLL_test
Output Code
Binary code
Gray code
Differential encoded binary
Differential encoded gray
Standard Data Output Timing
Third and fourth
Fourth and fifth
Fifth and sixth
Sixth and seventh
D4 D3 D2 D1 D0
MON
STD2[15:8] (H)
D12 D11 D10 D9 D8
Gray_test Gray code