Renesas HD49335HNP Specification Sheet page 12

HD49335NP/HNP
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Digital output
(D0 to D9)
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADC_in
ADCLK
D0 to D9
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
Table 9 Timing Specifications when ADCIN Input Mode is Used
No. Timing
(1) Signal fetch time
(2), (3) ADCLK t min./t
WH
(4) ADCLK rising to digital output hold time
(5) ADCLK rising to digital output delay time
Rev.1.0, Feb.12.2004, page 12 of 29
ADC
Clamp Level
data
ADCLK 2 clock
Figure 5 Detailed Timing Specifications at Pre-Blanking
(2)
min.
WL
ADCLK 10 clock
(1)
(3)
(4)
(5)
Symbol Min
t —
ADC1
Typ × 0.85
t
ADC2, 3
t —
AHLD4
t —
AOD5
Vth
V
OH
ADC
data
V
OL
Vth
V /2
DD
Typ Max
(6) —
Typ × 1.15
1/2f
ADCLK
(14.5) —
(23.5) —
Unit
ns
ns
ns
ns