Renesas HD49335HNP Specification Sheet page 27

HD49335NP/HNP
Example of Recommended External Circuit
Slave mode
Pin 57(Test1 = Low)
47
3.0V
47/6
47
to V.Baff
to CCD
33k
0.1
0.1
0.1
47
Master mode
Pin 57(Test1 = Hi)
47
3.0V
47/6
47
to V.Baff
to CCD
33k
0.1
0.1
0.1
47
Rev.1.0, Feb.12.2004, page 27 of 29
+
0.1
32 31 30 29 28 27 26
XV3
33 XV4
CH1
34
CH2
35
CH3
36
CH4
37
XSUB
38
SUB_SW/ADCK_in
39
40 SUB_PD
HD49335
STROB/Vgate
41
DV 3
42
SS
43 AV
SS
ADC_in
44
BIAS
45
46 VRB
47 VRT
VRM
48
AV
DD
49 50 51 52 53 54 55
+
1
0.1 47/6 1
1000p
CCD signal input
+
0.1
32 31 30 29 28 27 26
XV3
XV4
33
CH1
34
35 CH2
CH3
36
CH4
37
38 XSUB
SUB_SW/ADCK_in
39
SUB_PD
40
HD49335
STROB/Vgate
41
DV 3
42
SS
AV
43
SS
ADC_in
44
45 BIAS
VRB
46
VRT
47
48 VRM
AV
DD
49 50 51 52 53 54 55
+
1
0.1 47/6 1
1000p
CCD signal input
Pin 57 Mode
Low Slave mode
Hi Master mode
to CCD Pin 56 = Low: TESTIN mode. Please do not use.
Reset(Normally Hi)
25 24 23 22 21 20 19 18 17
VD_in
HD_in 16
CLK_in
15
DV 3
14
SS
DV 2
13
DD
D9
12
D8
11
D7
10
D6 9
D5
8
D4
7
D3 6
D2
5
D1
4
D0 3
DV 1,2 2
SS
ID
1
SCK
56 57 58 59 60 61 62 63 64
0.1 47/6
100p
Serial data input
to CCD
Reset(Normally Hi)
25 24 23 22 21 20 19 18 17
VD_in
HD_in
16
CLK_in
15
DV 3 14
SS
DV 2
13
DD
D9
12
D8 11
D7
10
D6
9
D5
8
D4
7
D3
6
D2
5
D1 4
D0
3
DV 1,2
2
SS
ID 1
SCK
56 57 58 59 60 61 62 63 64
0.1 47/6
100p
Serial data input
Specification
CLK, HD, VD input from SSG.
HD, VD output
0.1
from
Pulse generator
to
Camera
signal
processor
ID pulse
61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi: Pin 41 is Vgate output
Pin 39 is Hiz
0.1
to
Camera
signal
processor
from
Pulse generator
to
Camera
signal
processor
ID pulse
61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi: Pin 41 is Vgate output
Pin 39 is Hiz
Unit: R:
C: F