Renesas HD49335HNP Specification Sheet page 21

HD49335NP/HNP
Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 11 indicates the timing specifications.
10
ADC
Standard data
control signal
(D12,D11,D10)
ADCLK
OBP
(In case of select the positive polar)
Digital output
To use differential code, complex circuit is necessary at DSP side.
From ADC
Standard data
control signal
Address
1 1 1 1 0
Address
1 1 1 1 1
Rev.1.0, Feb.12.2004, page 21 of 29
Differential SW(D9)
+
2clk_DL
Carry bit
round
Figure 10 Differential Code, Gray Code Circuit
(In case of select the positive edge of ADCLK with D12)
(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)
1
Differential data
Figure 11 Differential Code Timing Specifications
Carry bit
round
Gray
Binary
(1) Differential coded
Figure 12 Complex Circuit Example
1 0 1 D7 D6 D5
P_RG P_ADCLK
0 0 0 D6 D5
P_SP2
Gray SW(D8)
Standard
data
selector
2 3 4 5
Standard
data
Standard
data
selector
2clk_DL
(2) Gray
STD1[7:0] (L)
D4 D3 D2 D1 D0
P_SP2 P_SP1
STD1[7:0] (L)
D4 D2 D1 D0
P_SP1 2,3 divided
select
10-bit
output
Gray Binary
conversion
6 7 8 9 10
Differential data
D11 D11
D10
D10
D9
D9
D0
D0
Binary conversion
STD2[15:8] (H)
D12 D11 D10 D9 D8
DLL
current
STD2[15:8] (H)
D15 D14 D13 D12 D10
P_RG
11
DLL
steps
D9 D8
P_ADCLK