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HD49335NP/HNP
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8
Timing Specifications when the CDSIN Input Mode is Used
No.
Timing
(1)
Black-level signal fetch time
(2)
SP1 'Hi' period
(3)
Signal-level fetch time
(4)
SP2 'Hi' period
(5)
SP1 falling to SP2 falling time
(6)
SP1 falling to ADCLK rising inhibit time
(7), (8)
ADCLK t
min./t
WH
(9)
ADCLK rising to digital output
(10)
ADCLK rising to digital output delay time
(11)
H1 rising to ADCLK rising time
(12)
H1 rising to SPSIG falling time
(13)
H1 rising to SPBLK falling time
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
CDS_in
OBP
Note:
1. Shifts 1 clock cycle depending on the OBP input timing.
Rev.1.0, Feb.12.2004, page 11 of 29
Black
level
CDS_in
(2)
SP1
SP2
(7)
ADCLK
D0 to D9
(11)
(12)
(13)
H1
min
WL
holding time
N
N+1
OB pulse > 2 clock cycles
Figure 4 OBP Detailed Timing Specifications
Signal
level
(3)
(1)
(5)
(4)
(6)
(8)
(9)
(10)
Symbol
Min
t
—
CDS1
Typ × 0.8
t
CDS2
t
—
CDS3
Typ × 0.8
t
CDS4
Typ × 0.85
t
CDS5
t
—
CDS6
t
11
CDS7, 8
t
—
CHLD9
t
—
COD10
t
—
CDS11
t
—
CDS12
t
—
CDS13
1
OB period *
N+5
Vth
Vth
Vth
Typ
Max
(1.5)
—
Typ × 1.2
1/4f
CLK
(1.5)
—
Typ × 1.2
1/4f
CLK
Typ × 1.15
1/2f
CLK
(5)
—
—
—
(7)
—
(16)
—
(1/4f
)
—
CLK
(1/f
)
—
CLK
(1/2f
)
—
CLK
N+12
N+13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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