Pin Arrangement; Pin Description - Renesas HD49335HNP Specification Sheet

HD49335NP/HNP

Pin Arrangement

AV
BLKC
CDS_in
AV
BLKFB
BLKSH
AV
Test2
Test1
DLL_C
DV
MON
41cont
SDATA

Pin Description

Pin No. Symbol Description
1 ID Odd/even number line detecting pulse output pin
2 DV 1,2 CDS Digital ground + ADC output buffer ground (0 V)
SS
3 to 12 D0 to D9 Digital output (D0; LSB, D9; MSB)
13 DV 2 ADC output buffer power supply (3 V)
DD
14 DV 3 General ground for TG (0 V)
SS
15 CLK_in CLK input (max 72 MHz)
16 HD_in HD input
17 VD_in VD input
18 Reset Hardware reset (for DLL reset)
19 RG Reset gate pulse output
20 DV 3 General power supply for TG (3 V)
DD
21 DV 4 H1 buffer power supply (3 V)
DD
22 H1A H.CCD transfer pulse output-1A
23 1/2clk_o CLK_in 2 divided output. 3 divided output at 3 divided mode
24 DV 4 H1 buffer ground (0 V)
SS
25 DV 4 H1 buffer ground (0 V)
SS
26 H2A H.CCD transfer pulse output-2A
27 1/4clk_o CLK_in 4 divided output. 6 divided output at 3 divided mode
28 DV 4 H2 buffer power supply (3 V)
DD
29 DV 3 General power supply for TG (3 V)
DD
Rev.1.0, Feb.12.2004, page 2 of 29
48 47 46 45 44 43 42 41 40
49
DD
50
51
52
DD
53
54
55
SS
56
57
58
1 59
DD
60
61
CS 62
63
SCK 64
1 2 3 4 5 6 7 8 9
39 38 37 36 35 34 33
10 11 12 13 14 15 16
(Top view)
32 XV3
31 XV2
30 XV1
29 DV 3
DD
28 DV 4
DD
27 1/4clk_o
26 H2A
25 DV 4
SS
24 DV 4
SS
23 1/2clk_o
22 H1A
21 DV 4
DD
20 DV 3
DD
19 RG
18 Reset
17 VD_in
Analog(A) or
I/O Digital(D) Remarks
O D 2 mA/10 pF
— D
O D 2 mA/10 pF
— D
— D
I D
I/O D
I/O D
I D Schmitt trigger
O D 3 mA/10 pF
— D
— D
O D 30 mA/165 pF
O D 2 mA/10 pF
— D
— D
O D 30 mA/165 pF
O D 2 mA/10 pF
— D
— D