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HD49335NP/HNP
CDS single operating mode
Pin 56(Test2 = Low) Pin 57 is "Don't care" in this mode.
47
3.0V
47
ADC_in
47
Serial data when CDS single operation mode are following resister specifications.
(Latch timing specification is same as normal mode)
CS
t
INT1
SCK
tsu
SDATA
Resister 0
D00
Low
0
D01
Low
0
D02
Low
0
D03
X
0
D04
X
0
D05
PGA(0) LSB
0
D06
PGA(1)
0
D07
PGA(2)
0
D08
PGA(3)
0
D09
PGA(4)
0
D10
PGA(5)
0
D11
PGA(6)
0
D12
PGA(7) MSB
0
D13
Test_I1 (0)
0
D14
Test_I1 (1)
0
D15 Test_I1 (2)
1
Rev.1.0, Feb.12.2004, page 28 of 29
+
47/6
0.1
32
31
30
29
28
27
26
33
34
35
PBLK
36
37
OBP
CP_DM
38
ADCK
39
SP2
40
SP1
41
DV
3
42
SS
AV
43
SS
44
ADC_in
BIAS
33k
45
VRB
0.1
46
0.1
VRT
47
0.1
48
VRM
AV
DD
49
50
51
52
53
54
55
+
1
0.1
47/6
1
1000p
CCD signal input
fsck
tho
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
Resister 1
Resister 2
Resister 3
High
1
Low
0
Low
0
High
1
Low
0
Low
0
Low: Normal
SLP
0
Clamp(0)
1
High: Sleep
Low: Normal
STBY
0
Clamp(1)
0
High: Standby
Output mode(LINV)
0
Clamp(2)
0
Output mode(MINV)
0
Clamp(3)
1
Output mode(Test0)
0
Clamp(4)
0
SHA-fsel(0)
0
HGstop-Hsel(0)
0
SHA-fsel(1)
0
HGstop-Hsel(1)
0
SHSW-fsel(0)
0
HGain-Nsel(0)
0
SHSW-fsel(1)
0
HGain-Nsel(1)
0
Low: Normal
SHSW-fsel(2)
0
LoPwr
1
High: Low power
SHSW-fsel(3)
0
X
0
Low:CDSin
Test_I2 (0)
0
ADSEL
0
High:ADin
Low: Reset
0
1
Test_I2 (1)
Reset
High: Normal
Reset(Normally Hi)
25
24 23 22 21 20 19 18 17
16
15
DV
3
14
SS
DV
2
13
DD
D9
12
D8
11
D7
10
D6
9
HD49335
D5
8
D4
7
D3
6
D2
5
D1
4
D0
3
DV
1,2
2
SS
1
SCK
56
57 58 59 60 61 62 63 64
0.1
100p
Serial data input
Resister 4
Resister 5
High
1
Low
0
High
High
1
Low
0
Low
Low
0
High
1
High
0
MON(0)
0
P_SP1(0)
0
MON(1)
0
P_SP1(1)
0
MON(2)
0
P_SP2(0)
0
H12Baff(0)
0
P_SP2(1)
0
H12Baff(1)
0
P_ADCLK(0)
0
H12Baff(2)
0
P_ADCLK(1)
0
H12Baff(3)
1
P_RG(0)
test
0
VD latch
0
P_RG(1)
0
Gray1
0
DLL_CK(0)
0
0
Gray2
DLL_CK(1)
0
0
Gray_ts(0)
DLL_CK(2)
0
Gray_ts(1)
0
DLL_CK(3)
0
0
Gray_ts(2)
DLL_current
0.1
to
Camera
signal
processor
Pin changes are not effective with pin61.
47/6
Unit: R:
C: F
t
INT2
Resister 6
Resister 7
1
Low
0
High
1
0
High
1
High
1
1
High
1
High
1
1
DL_SP1(0)
0
DL_RG_r(0)
0
0
DL_SP1(1)
0
DL_RG_r(1)
0
1
DL_SP1(2)
0
DL_RG_r(2)
0
1
DL_SP1(3)
0
DL_RG_r(3)
0
1
DL_SP2(0)
0
DL_RG_f(0)
0
0
DL_SP2(1)
0
DL_RG_f(1)
1
0
DL_SP2(2)
0
DL_RG_f(2)
0
0
DL_SP2(3)
0
DL_RG_f(3)
1
1
DL_ADCLK(0)
0
DMCG(0)
0
0
DL_ADCLK(1)
0
DMCG(1)
0
1
DL_ADCLK(2)
0
Dummy CP(0)
0
DL_ADCLK(3)
Dummy CP(1)
1
0
0
1
0
0
CDS_test
Dummy CP(2)
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