Reference Design Modifications - Xilinx KCU105 User Manual

• GUI front end graphical display of statistics collected from the underlying driver
through the driver interface.
The TRD demonstrates the use of PCIe in control plane applications. A simple kernel driver
on a host computer demonstrates BAR-mapped single double word (DW) register transfers.
Apart from generic GUI functionality described previously, the GUI allows you to read from
or write to BAR-mapped registers in hardware and display them in a GUI window.

Reference Design Modifications

Adding a pre-built additional AXI block RAM controller is included in the TRD as an
extension of the base design. This section describes how to add an additional AXI block
RAM controller to the design and set up ingress translations through BAR4 to access this
memory space.
Rebuilding Hardware
A pre-built design script is provided that can be run to generate a bitstream with an
additional AXI block RAM controller added. The additional block RAM is mapped to AXI
address 0xD000_0000. The steps needed to build the user modification design are
described in Chapter 4, Implementing and Simulating the
Software Modification
The pre-built user extention design can be tested only on Linux and not on Windows.
IMPORTANT:
There is no support for the user extension design in the Windows platform.
In the software driver, access to newly added block RAM can be added as follows.
In the file software/linux_driver_app/driver/ctrlplane/xpcie.c, under the
InitBridge function, the line can be changed as shown:
//- Program DST address to be AXI domain address for BRAM Controller
XIo_Out32((bar0_addr +REG_BRDG_BASE + REG_INGR_AXI_BASE + SECOND_TRANS
+OFFSET_INGR_AXI_DST_LO ), 0xC0000000);
//- Program DST address to be AXI domain address for BRAM Controller
XIo_Out32((bar0_addr +REG_BRDG_BASE + REG_INGR_AXI_BASE + SECOND_TRANS
+OFFSET_INGR_AXI_DST_LO ), 0xD0000000);
This maps the newly added block RAM controller to BAR4. With this minor change, the
same GUI can be used for read/write access.
PCI Express Control Plane TRD
UG918 (v2017.2) July 18, 2017
Chapter 5: Targeted Reference Design Details and Modifications
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