Xilinx KCU105 User Manual page 36

Endpoint Block for PCI Express
The PCI Express IP for is used in the following configuration:
• x1 Gen1 line rate (2.5 GT/s/lane/direction)
• Three 64-bit BARs
See LogiCORE IP UltraScale FPGAs Gen3 Integrated Block for PCI Express Product Guide
(PG156) [Ref 4]
DMA Bridge Core
The DMA bridge core includes an AXI-PCIe bridge and Expresso DMA in one netlist bundle.
See the Northwest Logic Expresso DMA Bridge Core website to obtain a user guide
The IP netlist used in the reference design supports a fixed configuration where the number
Note:
of DMA channels and translation regions is fixed; for higher configurations of the IP, contact
Northwest Logic.
The Northwest Logic Expresso IP provided with the design is an evaluation version of the IP.
Note:
It times out in hardware after 12 hours. To obtain a full license of the IP, contact Northwest Logic.
AXI-PCIe Bridge
The AXI-PCIe bridge translates protocol to support transactions between the PCIe and AXI3
domains. It provides support for two ingress translation regions to convert PCIe
BAR-mapped transactions to AXI3 domain transactions.
Bridge Initialization
The AXI-PCIe bridge consumes transactions hitting BAR0 in the Endpoint.
• The bridge registers are accessible from BAR0 + 0x8000.
• During ingress translation initialization:
Two ingress translations are enabled (0x800 and 0x820).
°
Address translation is set up as shown in
°
For example, assume that the PCIe BAR2 physical address is 0x2E000000. Any memory
read request targeted to address 0x2E000000 is translated to 0x44A00000.
Table 5-1: Address Translation Maps
Ingress Source Base
BAR2
BAR4
PCI Express Control Plane TRD
UG918 (v2017.2) July 18, 2017
Chapter 5: Targeted Reference Design Details and Modifications
for more information.
Ingress Destination Base
0x44A00000
0xC0000000
www.xilinx.com
Table 5-1.
Comments
PCIe BAR2 mapped to power monitor slave
PCIe (BAR4) mapped to AXI block RAM
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[Ref 5].
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