Features - Xilinx KCU105 User Manual

An Expresso DMA Bridge Core from Northwest Logic (NWL)
PCIe-to-AXI conversion of transactions. The downstream slaves include a power, voltage,
and temperature (PVT) module monitoring parameters from the FPGA system monitor and
AXI block RAM IP targeted to BARs.

Features

The TRD includes these features:
• PCIe x1 Gen1 Endpoint operating at 2.5 GigaTransfers per second (GT/s) per
lane/direction
Single physical function with support for three 64-bit BARs
°
• DMA Bridge IP Core
Ingress address translation capability
°
AXI3 interface
°
• 64-bit kernel space drivers for Linux and Windows 7, which run on the host computer
• Control and monitoring graphical user interface (GUI)
Resource Utilization
Table 1-1 and Table 1-2
synthesis. Place and route can alter these numbers based on placements and routing paths.
These numbers are to be used as a rough estimate of resource utilization. These numbers
might vary based on the version of the TRD and the tools used to regenerate the design.
Table 1-1: Base Design Resource Utilization
Resource Type
CLB registers
CLB LUT
Block RAM
MMCME3_ADV
Global Clock Buffers
BUFG_GT
SYSMONE1
IOB
PCI Express Control Plane TRD
UG918 (v2017.2) July 18, 2017
list the resources used by the base and user extension designs after
Available
484,800
242,400
600
10
240
120
1
520
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Chapter 1: Introduction
[Ref 1] is used to demonstrate
Used Usage (%)
43,896
27,431
22
1
3
5
1
16
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9.05
11.32
3.66
10
1.25
4.17
100
3.08
6